Design and test workflow for next-gen storage

Design and test workflow for next-gen storage

With a comprehensive workflow solution, Keysight aims to make product development for memory systems based on Double Data Rate 5 (DDR5), Low-Power Double Data Rate 5 (LPDDR5) and Graphics Double Data Rate 6 (GDDR6) technologies more secure while reducing development time.

From cloud computing to autonomous vehicles, the demand for faster memory interfaces continues to grow in all fields of application. A breakthrough technological feature of fast interfaces such as DDR5, LPDDR5 and GDDR6 is equalization at the receivers of the memory chip, which restores signals that have been degraded on their way through the printed circuit board (PCB). Hardware engineers need to minimize the risk of signal integrity issues in memory bus designs. To do this, they need to be able to predict signal quality after equalization, prototype the design and test performance. The new PathWave ADS 2022 simulation software reduces these risks in product development for these memory systems as well as the development time required.

The design and test workflow for next-generation memory enables hardware developers to meet time-to-market requirements and deliver a high-performance, reliable end product. The Memory Designer in PathWave ADS 2022 addresses the following design challenges:

  • Accurate modeling of transmitter and receiver behavior by generating advanced simulation models of DDR transmitters and receivers, with flexible equalization and external clock inputs.
  • Optimized equalization settings to predict design margins with an advanced simulator that uses adaptive equalization to find the optimal settings for the best data link signal integrity.
  • Quantified margins for the eye mask by predicting eye closure down to standard specific bit error rates and displaying the remaining margin for the eye mask.
  • Finding faulty conditions with the design investigation by generating a batch simulation list to run through all possible design parameters and display the passed/faulty configurations as spreadsheet data.

As a result, this design-to-test workflow provides confidence in the release of the design. Running an automated conformance report for simulated waveforms and using consistent measurement techniques allows problems to be identified early and potential fixes to be tested efficiently.

"PathWave ADS' state-of-the-art signal integrity simulator helps Xilinx develop advanced system memories. By working with Keysight, we are able to optimize system memory solutions for our customers," said Thomas To, Director of System Memory SI at Xilinx.

Brig Asay, Director of Strategic Planning for the Internet Infrastructure Group at Keysight, states: "DDR5 is a revolutionary technology that is forcing designers to re-evaluate their simulation and measurement approaches. Our knowledge in both DDR5 simulation and measurement techniques allows us to help customers overcome this technological hurdle and get them to a first design success faster."

Keysight's advanced design and validation solutions help accelerate innovation. The company's commitment to speed and accuracy extends to software-driven insights and analytics that help bring tomorrow's technology products to market faster throughout the development lifecycle - including design simulation, prototype validation, automated software testing, manufacturing analytics and optimization of network performance and visibility in enterprise, service provider and cloud environments. The company's customers come from the communications, manufacturing, aerospace and defense, automotive, energy and energy technology, semiconductor and electronics manufacturing industries Keysight achieved a turnover of $4.2 billion in the 2020 financial year.

  • Issue: Januar
  • Year: 2020
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Fax: 07581 4801-10
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