Design optimization of IC layouts

Design optimization of IC layouts

Siemens Digital Industries Software introduces Calibre DesignEnhancer, a software that increases productivity, improves design quality and shortens time-to-market for place-and-route (P&R) applications and customized designs.

Design optimization is achieved by automatically implementing 'Calibre Correct-by-Construction' layout changes early in the IC design and verification process.

The Calibre DesignEnhancer tool is the latest in a series of shift-left tools for the Calibre nm platform for physical verification of ICs. It enables the enhancement of custom and digital designs and physical verification. It optimizes designs quickly and accurately to reduce or eliminate voltage drop (IR) and electromigration (EM) issues. By automating layout optimization during the design and implementation phases, the Calibre DesignEnhancer tool helps bring DRC-correct (design rule checking) designs to tape-out faster and improve circuit reliability.

The DesignEnhancer tool integrates with all major design and implementation environments via industry interfaces. Kits are available for all leading foundries. They support designs from 130 to 2 nm.

 

  • Issue: Januar
  • Year: 2020
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Eugen G. Leuze Verlag GmbH & Co. KG
Karlstraße 4
88348 Bad Saulgau

Tel.: 07581 4801-0
Fax: 07581 4801-10
E-Mail: info@leuze-verlag.de

 

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